A method of manufacturing a three-dimensionally mounted IC by transferring, to a handle substrate, a semiconductor layer having a complementary metal oxide semi-conductor (CMOS) circuit formed therein is known. According to an example of such a method, a release layer composed of porous silicon is formed on a surface of a silicon wafer, a semiconductor layer composed of single-crystal silicon is epitaxially grown on the release layer, and a CMOS circuit is then formed in the semiconductor layer.
Subsequently, the semiconductor layer having the CMOS circuit formed therein is bonded to a handle substrate. Separation is conducted at the release layer to transfer the semiconductor layer to the handle substrate. This process is repeated a plurality of times to stack a plurality of semiconductor layers each having the CMOS circuit formed therein on the handle substrate.
Patent Literature 1 discloses a process in which a semiconductor layer having a transistor formed therein is bonded to a handle wafer having a back-side recess, with a polymer film therebetween, and the semiconductor layer is transferred to the handle wafer. This process is then repeated to form stacked transistors.
Patent Literature 2 describes a method of manufacturing a semiconductor chip including a first semiconductor chip and a second semiconductor chip that are arranged so that surfaces each having bonding pads thereon face each other, and a large number of through-silicon vias formed in each of the first and second semiconductor chips.